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Device simulations are used to gain insights on the design of nanoscale thin-buried-oxide (and ultrathin-body) fully depleted/silicon-on-insulator (SOI) CMOS and to assess its scalability toward the end of the Semiconductor Industry Association roadmap (International Technology Roadmap for Semiconductors), relative to that of FinFET CMOS. The simulation results imply, albeit with complex processing, good scalability and performance for low-power (LP) applications (including static random access memory), defined by minimum viable SOI thickness. However, the scalability for high-performance (HP) applications is limited, but the processing can be simplified. Results for double-gate FinFETs are better, showing good scalability and performance to the end of the ITRS for both HP and LP applications.