By Topic

A power-efficient prediction hardware architecture for H.264 decoding

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Xi Wang ; Inst. of Microelectron., Peking Univ., Beijing, China ; Xiaoxin Cui ; Dunshan Yu

Prediction, including intra prediction and inter prediction, is the most critical issue in H.264 decoding in terms of processing cycles and computation complexity. These two predictions demand a huge number of memory accesses and the total decoding cycles. In this paper, an efficient hardware architecture for real-time implementation of intra and inter predictions algorithm used in H.264 video coding standard is adopted. Compared with conventional architecture, the predict efficiency is enhanced. Under different prediction modes, our design is able to decode each macroblock (MB) within 500 cycles. The Verilog RTL of intra prediction is verified to work at 103 MHz and the inter prediction is verified to work at 81 MHz in a Xilinx II FPGA.

Published in:

Industrial Electronics and Applications (ICIEA), 2010 the 5th IEEE Conference on

Date of Conference:

15-17 June 2010