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A low power architecture design method based on DFG model

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2 Author(s)
Tingting Chen ; Coll. of Inf., Beijing Union Univ., Beijing, China ; Zheying Li

A low power architecture design method is brought forward by this paper based on DFG (Data Flow Graphic) model. Through this method, a DFG model is extracted from the logic model of a circuit or a system and is used to optimize the circuit architecture for reducing the power consumption of circuit. In this paper, the data transmission process of USB2.0 is taken as an example to prove the correctness of this low power architecture design method.

Published in:
Industrial Electronics and Applications (ICIEA), 2010 the 5th IEEE Conference on

Date of Conference: 15-17 June 2010

Page(s):
1711 - 1714
E-ISBN :
978-1-4244-5046-6
Print ISBN:
978-1-4244-5045-9
INSPEC Accession Number:
11433875
Conference Location :
Taichung
Digital Object Identifier :
10.1109/ICIEA.2010.5515249
Product Type:
Conference Publications

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