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Low power FPGA design using hybrid CMOS-NEMS approach

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3 Author(s)
Yu Zhou ; Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA ; Shijo Thekkel ; Swarup Bhunia

Higher integration density of nanoscale CMOS causes two major design challenges in SRAM-based Field Programmable Gate Array (FPGA) designs: large power dissipation (contributed by both leakage and dynamic power) and reduced reliability of operation. In this paper, we propose a hybrid design approach for SRAM-based FPGA that can leverage on non-volatile carbon nanotube based nano electro-mechanical systems (NEMS) switches for low static and dynamic power. Simulations show that the proposed CMOS-NEMS lookup table (LUT) based circuits can achieve a reduction of up to 91% in total power at iso-performance, compared to the conventional CMOS-based LUT circuits.

Published in:

Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on

Date of Conference:

27-29 Aug. 2007