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This article has designed a set of train communication network link layer and physical layer implementations. The program uses a top-down design method developed the FPGA and the ARM as the core of the circuit diagrams. The data between two pairs transmit by a dual-FIFO. By analyzing the existing implementation HDLC Protocol approach proposed HDLC protocol implementations using FPGA. And the use of FPGA on-chip all-digital phase-locked loop to extract the bit synchronous clock to achieve the Manchester encoding and decoding. In the finished making the actual PCB for the actual test, the results have verified the accuracy and reliability of the design.