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On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking

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4 Author(s)
Verbree, J. ; 3D Integration Program, IMEC vzw, Leuven, Belgium ; Marinissen, E.J. ; Roussel, P. ; Velenis, D.

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise high-performance low-power functionality in a smaller form factor at lower cost. Stacking entire wafers has attractive benefits, but unfortunately suffers from low compound stack yield, as one cannot prevent to stack a bad die to a good die or vice versa. Matching individual wafers from repositories of pre-tested wafers to each other is a simple yet effective method to significantly increase the compound stack yield. In this paper, we present a mathematical model, which shows that the yield increase depends on (1) the number of stack tiers, (2) the number of dies per wafer, (3) the die yield, and (4) the repository size. Simulation results demonstrate that, for realistic cases, relative yield increases of 0.5% to 10% can be achieved. We also show that the required investment, in terms of a limited increase in either test or package costs, is typically well justified.

Published in:

Test Symposium (ETS), 2010 15th IEEE European

Date of Conference:

24-28 May 2010