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A transient error tolerant self-timed asynchronous architecture

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2 Author(s)
Zamani, M. ; Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA ; Tahoori, M.B.

High runtime failure rate as a result of reliability detractors is one of the major challenges for scaled-CMOS as well as emerging nanotechnologies. This results in multiple faults during life time operation. In this paper we propose a self-timed asynchronous architecture which can tolerate multiple transient bit-flips. This architecture has self-timed property, making it robust against delay variations caused by increased process variations at nanoscale. The proposed architecture can achieve 100% tolerance of single transient faults as well as more than 93% tolerance of multiple faults for failure rate less than 10-2.

Published in:

Test Symposium (ETS), 2010 15th IEEE European

Date of Conference:

24-28 May 2010

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