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In this paper configurable fault tolerant links are proposed for inter-die communication in stacked 3D SoCs. For high TSV fault rates, links degrade their performance by serial data transmission and signal remapping on the defect free wires. The link degradation is limited to a predetermined value, above which the link is considered non-functional.
Test Symposium (ETS), 2010 15th IEEE European
Date of Conference: 24-28 May 2010