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A study of signal integrity issues in through-silicon-via-based 3D ICs

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2 Author(s)
Chang Liu ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Sung Kyu Lim

In this paper, we study the signal integrity issues of through-silicon-via (TSV)-based 3D IC layouts. Unlike the most existing work, our study reports the coupling noise among all nets and all TSVs used in a real processor design implemented in 3D. Our RTL-to-GDSII design flow consists of commercial tools, enhanced with various add-ons to handle TSV and 3D stacking. Using this tool flow, we generate GDSII-level layouts of 3D implementation and perform sign-off-level signal integrity analysis. Based on our 2D vs 3D GDSII comparisons, we found that the overall noise-level of 3D is worse than 2D, but 3D designs have the advantage of significantly reducing the total number of the nosiest nets.

Published in:

Interconnect Technology Conference (IITC), 2010 International

Date of Conference:

6-9 June 2010