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Design of A 10Gb/s in-line scalable Network Security Processor array

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3 Author(s)
Yun Niu ; Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China ; Liji Wu ; Jun Xu

Design of a Gigabit In-Line scalable Network Security Processor on one chip is presented. With 8 parallel chips array and some control logic, the design may be used in 10 Gigabit Ethernet. Moreover, custom-specific off-chip crypto algorithms can replace the standard one on the chip through pr-reserved data interface, which improves the scalability of the design in crypto operation.

Published in:

Wireless and Optical Communications Conference (WOCC), 2010 19th Annual

Date of Conference:

14-15 May 2010

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