By Topic

On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Biberman, A. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Chan, J. ; Bergman, K.

We examine the complex relationship between experimentally-measured power penalty performance metrics of a silicon photonic modulator, and its broad impact on the throughput performance of a full-scale on-chip optical interconnection network. Using our physically-accurate network-level simulation environment, we further evaluate this impact from hypothetical device performance improvements. The results indicate that in order to achieve the highest throughput, an intricate balance must be reached between modulation rate and device performance.

Published in:

Interconnect Technology Conference (IITC), 2010 International

Date of Conference:

6-9 June 2010