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Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the successful implementation of this process in circuit design and production. Most TSVs in these applications are copper (Cu) filled. Analysis of Cu-filled TSV induced stress has been reported by Okoro et. al, and the proposed stress measurement and model has been reported by Chidambaram et. al. Finite element method (FEM) 3D simulation has been used to model the localized stress fields at the surrounding substrate area for W-filled TSVs, and this simulation has been verifiably correlated to the CRM and EBSD measurement results. In this paper, to help in determining circuit layout design rules, FEM is extensively used in evaluating the impact of TSV size, length and spacing on the induced stress to the nearby silicon substrate.