By Topic

Through-Silicon-Via stress 3D modeling and design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Dao, T. ; Freescale Semicond., Austin, TX, USA ; Adams, V.

Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the successful implementation of this process in circuit design and production. Most TSVs in these applications are copper (Cu) filled. Analysis of Cu-filled TSV induced stress has been reported by Okoro et. al, and the proposed stress measurement and model has been reported by Chidambaram et. al. Finite element method (FEM) 3D simulation has been used to model the localized stress fields at the surrounding substrate area for W-filled TSVs, and this simulation has been verifiably correlated to the CRM and EBSD measurement results. In this paper, to help in determining circuit layout design rules, FEM is extensively used in evaluating the impact of TSV size, length and spacing on the induced stress to the nearby silicon substrate.

Published in:

IC Design and Technology (ICICDT), 2010 IEEE International Conference on

Date of Conference:

2-4 June 2010