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A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65 nm CMOS technology, show an operation bandwidth from 106 GHz to 128 GHz, with 6 mW core power dissipation. With 0 dBm input power, the output peak voltage swing, is 330 mV, at 115 GHz.
Date of Conference: 2-4 June 2010