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ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs

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10 Author(s)
Wang, A. ; Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA ; Xiaokang Guan ; Siqiang Fan ; He Tang
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Electrostatic discharge (ESD) failure is a major reliability problem, and ESD protection is an emerging design challenge for radio-frequency (RF) integrated circuits demanding extremely high reliability for wireless applications in harsh environments. This paper reports the design and optimization of a 5-kV ESD-protected 2.4-GHz power amplifier (PA) circuit in a 0.18-μm RFCMOS technology. A new mixed-mode ESD simulation-design method and an accurate RF ESD characterization technique are used to minimize the inevitable ESD-induced parasitic effects, which can significantly degrade PA circuit performance. A novel ESD-aware PA design technique is utilized to optimize whole-chip ESD+PA performance. Experiments show that conventional ESD protection can seriously affect the PA circuit, while optimized ESD protection may resolve such a problem. The optimized ESD-protected PA circuit achieves good whole-chip performance, including 5-kV ESD protection, a linear output of 13.5 dBm, a gain of 20.2 dB, and a power-added efficiency of ~ 18%, all favorable in the same design category.

Published in:

Industrial Electronics, IEEE Transactions on  (Volume:58 ,  Issue: 7 )

Date of Publication:

July 2011

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