By Topic

A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hyunbean Yi ; Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA ; Kundu, S. ; Sangwook Cho ; Sungju Park

This brief presents a design-for-debug technique for a system-on-a-chip with multiple clock domains. We describe the debugging limitations that can exist between different clock domains when performing a scan-based debug methodology and then propose a scan cell and debug control logic to address those limitations. The proposed scan cell is designed to hold and shift the current or the previous state and support online debug. The debug control logic optimizes a core test infrastructure such as the IEEE 1500 test wrapper to minimize area overhead.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:57 ,  Issue: 7 )