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Memory access dependencies in shared-memory multiprocessors

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2 Author(s)
M. Dubois ; Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA ; C. Scheurich

The presence of high-performance mechanisms in shared-memory multiprocessors such as private caches, the extensive pipelining of memory access, and combining networks may render a logical concurrency model complex to implement or inefficient. The problem of implementing a given logical concurrency model in such a multiprocessor is addressed. Two concurrency models are considered, and simple rules are introduced to verify that a multiprocessor architecture adheres to the models. The rules are applied to several examples of multiprocessor architectures

Published in:

IEEE Transactions on Software Engineering  (Volume:16 ,  Issue: 6 )