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Photonic Chip-Scale Interconnection Networks for Performance-Energy Optimized Computing

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1 Author(s)
Bergman, K. ; Columbia Univ., New York, NY, USA

As chip multiprocessors (CMPs) scale to increasing numbers of cores and greater on-chip computational power, the gap between the available off-chip bandwidth and that which is required to appropriately feed the processors continues to widen under current memory access architectures. For many high-performance computing applications, the bandwidth available for both on- and off-chip communications can play a vital role in efficient execution due to the use of data-parallel or data-centric algorithms. Electronic interconnected systems are increasingly bound by their communications infrastructure and the associated power dissipation of high-bandwidth data movement. Recent advances in chip-scale silicon photonic technologies have created the potential for developing optical interconnection networks that can offer highly energy efficient communications and significantly improve computing performance-per-Watt. This talk will examine the design and performance of photonic networks-on-chip architectures that support both on-chip communication and off-chip memory access in an energy efficient manner.

Published in:

Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on

Date of Conference:

3-6 May 2010

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