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Performance Evaluation of a Multicore System with Optically Connected Memory Modules

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4 Author(s)
Paul Vincent Mejia ; Dept. of Electr. & Comput. Eng., Univ. of California Davis, Davis, CA, USA ; Rajeevan Amirtharajah ; Matthew K. Farrens ; Venkatesh Akella

Over the past years, there have been impressive advances in bandwidth, latency, and scalability of on-chip networks. However, unless the off-chip network bandwidth and latency are also improved, we might have unbalanced systems which will limit the improvements to overall system performance. In this paper, we show how dense wavelength-division multiplexing (DWDM) -based optical interconnects could be used to emulate multiple buses in a fully-buffered DIMM (FB-DIMM) -like memory system to improve both bandwidth and latency. We evaluate an optically connected memory using full-system simulations of an 8-core system running memory-intensive multithreaded workloads. We show that for the FFT benchmark, optically connected memory can reduce the average memory request latency by 29% compared to a single-channel DDR3 SDRAM system and provide an overall performance speedup of 1.20. We also show that at least two DDR3 memory channels are needed to match the performance of a single optical bus, which demonstrates the advantage of optical interconnects in terms of savings in the number of pins required.

Published in:

Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on

Date of Conference:

3-6 May 2010