By Topic

Digital Synchronous System for Ultra High-Speed Physical Diagnostic Equipments

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yingdong Xue ; Xi''an Inst. of Opt. & Precision Mech., Chinese Acad. of Sci., Xi''an, China ; Yong-Lin Bai ; Yan Li

A design of the digital synchronous system which is based on FPGA is presented. To reduce the delay of the system logic and enhance the working frequency, the timing constraints have been analyzed. We investigate the influences of the delay of data output (Tco), the delay of combinational logic circuits (Tdelay), the setup time (Tsetup) and the clock cycle (T) on the working frequency, and adopt the method of combinational logic splitting to reduce the LUT cascade connection. As a result, not only is stably running the system at 200 MHz clock realized, but also completely meets the experiment requirements. This system provides a reliable guarantee for controlling on ultra high-speed physical diagnostic system.

Published in:

Photonics and Optoelectronic (SOPO), 2010 Symposium on

Date of Conference:

19-21 June 2010