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A design of the digital synchronous system which is based on FPGA is presented. To reduce the delay of the system logic and enhance the working frequency, the timing constraints have been analyzed. We investigate the influences of the delay of data output (Tco), the delay of combinational logic circuits (Tdelay), the setup time (Tsetup) and the clock cycle (T) on the working frequency, and adopt the method of combinational logic splitting to reduce the LUT cascade connection. As a result, not only is stably running the system at 200 MHz clock realized, but also completely meets the experiment requirements. This system provides a reliable guarantee for controlling on ultra high-speed physical diagnostic system.