Nickel-Silicide Contact Technology With Dual Near-Band-Edge Barrier Heights and Integration in CMOS FinFETs With Single Mask

This letter reports the demonstration of a nickel-silicide contact technology that achieves dual near-band-edge barrier heights (i.e., a low electron barrier height Φ
Bn
for n-FETs and a low hole barrier height Φ
Bp
for p-FETs) using just one additional masking and two ion-implant steps. Independent and effective tuning of contact resistance
RC
is achieved in both p- and n-FinFETs. The compensation effect of aluminum and sulfur implants is studied for the first time and exploited for process simplification. A novel cost-effective integration scheme is shown to give significant
I
_DSAT
enhancement for p- and n-FinFETs.