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Design of A 100MHz – 1.66GHz, 0.13µm CMOS phase locked loop

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5 Author(s)
Ayat, M. ; Dept. of Electr. Eng., Iran Univ. of Sci. & Technol., Tehran, Iran ; Babaei, B. ; Atani, R.E. ; Mirzakuchaki, S.
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A fully integrated charge-pump phase-locked loop (PLL) is described. The PLL is designed and simulated in a 0.13 CMOS technology. The PLL lock range is from 100MHz to 1.66GHz.

Published in:

Electronic Devices, Systems and Applications (ICEDSA), 2010 Intl Conf on

Date of Conference:

11-14 April 2010