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A new systolic design for digital IIR filters

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1 Author(s)
Jayadeva ; Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India

Two systolic implementations of digital IIR filters are presented and compared with the designs of W. Luk and G. Jones (1988). It is shown that they represent a general class of systolic filters which reduce to canonical delay implementations in the limit

Published in:

Circuits and Systems, IEEE Transactions on  (Volume:37 ,  Issue: 5 )

Date of Publication:

May 1990

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