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Corrections to “Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect” [May 10 689-696]

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4 Author(s)

In the above titled paper (ibid., vol. 18, no. 5, pp. 689-696, May 10), the formula and the caption in Fig. 3 appeared incorrectly. The correct figure is presented here along with an explanation.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 8 )