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Optimization of viterbi decoder parameters for WRAN system

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2 Author(s)
Ahmadi, M. ; ECE Dept., Univ. of Tehran, Tehran, Iran ; Sied Mehdi Fakhraie

Extracting the fixed point model for digital hardware implementation is an important step in the realization of digital signal processing systems. In such a model, limited word lengths for processing blocks should be selected with no harmful effects on the system performance. Viterbi decoder is one of the commonly used blocks in digital communication systems. Optimizing its word length causes a considerable reduction in the chip area and decoding delay. In this paper the Viterbi decoder parameters, i.e. the number of soft decision bits and trace-back depth, are optimized for a new wireless standard, IEEE 802.22. The optimization is performed with less than 0.5 dB degradation of BER of the fixed point model compared to the floating point model. The 64-QAM modulation with the code rate 5/6 is selected as a case study since it is the most sensitive mode in the standard to the channel noise. Simulation results show that the Viterbi decoder with 7 bit soft decision and trackback depth of 70 meets the system requirements.

Published in:

Future Computer and Communication (ICFCC), 2010 2nd International Conference on  (Volume:3 )

Date of Conference:

21-24 May 2010