A Comparative Evaluation of High-Level Hardware Synthesis Using Reed–Solomon Decoder

Using the example of a Reed–Solomon decoder, we provide insights into what type of hardware structures are needed to be generated to achieve specific performance targets. Due to the presence of run-time dependencies, sometimes it is not clear how the C code can be restructured so that a synthesis tool can infer the desired hardware structure. Such hardware structures are easy to express in an HDL. We present an implementation in Bluespec, a high-level HDL, and show a 7.8
$\times$
improvement in performance while using only 0.45
$\times$
area of a C-based implementation.