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Real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator for a multi-media SoC

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3 Author(s)
Higuchi, R. ; Renesas Technol. Corp., Itami, Japan ; Teraoka, E. ; Higashida, M.

Latest multi-media SoCs used in a digital product such as digital TV have a structure where a number of IPs with real-time requirement share one channel of off-chip SDRAM using high-frequency bus to achieve multi-function, high-performance, and low-cost. Thus, such a bus system is required that satisfies real-time requirement, realizes high-efficiency, and has hierarchical structure. In this bus system, bus arbitration plays a crucial role. In this paper, we show Static arbitration has an advantage in bus efficiency over existing arbitration algorithms. And we propose a real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator and the Priority Level Transmission Mechanism. Simulation results show that the proposed bus system can satisfy real-time requirement, and is practical and efficient.

Published in:

VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on

Date of Conference:

26-29 April 2010

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