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Model reduction techniques for the formal verification of hardware dependent software

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5 Author(s)
Ecker, W. ; Infineon Technol., Hagenberg, Austria ; Esen, V. ; Findenig, R. ; Steininger, T.
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Contemporary researches provide many solutions for formally verifying both hardware and software systems. In this paper, we describe the formal verification of assembly programs, which are part of the HW/SW interface in hybrid systems. We have developed several methods to model assembly programs in VHDL in order to verify their functionality. Our discussion will show that, by applying different reduction methods, we managed to formally verify the correctness of iterative algorithms with execution times higher than 6000 clock cycles.

Published in:

High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE International

Date of Conference:

10-12 June 2010