By Topic

A Galois field-based logic synthesis with testability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Mathew, J. ; Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK ; Jabir, A.M. ; Singh, A.K. ; Rahaman, H.
more authors

In deep-submicron very-large-scale integration (VLSI) systems, efficient circuit testability is one of the most demanding requirements. An automatic synthesis technique for designing efficiently testable logic circuits is one of the ways to tackle the problem. To this end, this study introduces the generalised theory and a new fast efficient graph-based decomposition technique for the functions over finite fields defined over the set GF(N), where N is a power of a prime number, which utilises the data structure of the multiple-output decision diagrams. In particular, the proposed technique can decompose any N valued arbitrary function over the fields conjunctively and disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to the existing approaches. Furthermore, the authors have shown that the basic block can be tested with only eight test vectors.

Published in:

Computers & Digital Techniques, IET  (Volume:4 ,  Issue: 4 )