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A Galois field-based logic synthesis with testability

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5 Author(s)
Mathew, J. ; Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK ; Jabir, A.M. ; Singh, A.K. ; Rahaman, H.
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In deep-submicron very-large-scale integration (VLSI) systems, efficient circuit testability is one of the most demanding requirements. An automatic synthesis technique for designing efficiently testable logic circuits is one of the ways to tackle the problem. To this end, this study introduces the generalised theory and a new fast efficient graph-based decomposition technique for the functions over finite fields defined over the set GF(N), where N is a power of a prime number, which utilises the data structure of the multiple-output decision diagrams. In particular, the proposed technique can decompose any N valued arbitrary function over the fields conjunctively and disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to the existing approaches. Furthermore, the authors have shown that the basic block can be tested with only eight test vectors.

Published in:

Computers & Digital Techniques, IET  (Volume:4 ,  Issue: 4 )

Date of Publication:

July 2010

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