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A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS

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6 Author(s)
Drago, S. ; NXP Semicond., Eindhoven, Netherlands ; Leenaerts, D. ; Nauta, B. ; Sebastiano, F.
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The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 x 0.15 mm2 and draws 200 μA from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 7 )