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A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity SOI substrate (3 kΩ · cm). The PA measurements are carried out for supply voltages VDD going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power-added efficiency (PAE) is higher than 20% for all applied VDD values.