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10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter

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4 Author(s)
Moo-Young Kim ; Electr. & Electron. Eng. Dept., Korea Univ., Seoul, South Korea ; Jinwoo Kim ; Tagjong Lee ; Chulwoo Kim

A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and-distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 × 0.8 mm2 of active area.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 8 )

Date of Publication:

Aug. 2011

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