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Hardware-Efficient Image-Based Robotic Path Planning in a Dynamic Environment and Its FPGA Implementation

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2 Author(s)
N. Sudha ; School of Computer Engineering, Nanyang Technological University, Singapore, Singapore ; Aruppukottai Rajarathinam Mohan

This paper presents a hardware-efficient algorithm and a very large scale integration architecture for finding a path for a mobile robot on the image of an environment captured by an overhead camera. The algorithm computes a distance map to identify the collision-free region for the robot and then constructs a breadth-first search tree to find a path in that region. The path obtained from a start point to the goal is the shortest path in terms of the number of steps. The time-critical part of the algorithm is mapped onto a 2-D cellular architecture that consists of a locally interconnected array of identical processing elements. In view of this local interconnection and regular structure, the architecture can be operated at high speed. An extension based on the assignment of multiple pixels to a processing element and processing them in pipeline is proposed to enhance the scalability of the design. The design has been implemented and evaluated on a Xilinx ML403 evaluation platform with Virtex-4 XC4VFX12 field-programmable gate array (FPGA). The maximum frequency of operation obtained is 375 MHz. This results in computing a collision-free path on images of size 100 × 100 in less than 27.6 μs. The FPGA design is capable of processing images at video rate for real-time path planning in a dynamic environment.

Published in:

IEEE Transactions on Industrial Electronics  (Volume:58 ,  Issue: 5 )