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A 65nm embedded low power SRAM compiler

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4 Author(s)
Sheng Wu ; Inst. of Microelectron., Tsinghua Univ., Beijing, China ; Xiang Zheng ; Zhiqiang Gao ; Xiangqing He

A highly flexible design methodology of Static Random Access Memory (SRAM) compiler platform is proposed in this paper. With this method, a 65nm CMOS embedded low power single-port SRAM compiler which can generate the whole SRAM IP module files has been developed. A reconfigurable semiautomatic design flow of compiler is obtained, which can be fit for any regular circuits and be more self-adaptive to the migration of technology nodes. According to the design flow, a dual-port SRAM compiler is produced in 65nm process.

Published in:

Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on

Date of Conference:

14-16 April 2010

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