Cart (Loading....) | Create Account
Close category search window

A 65nm embedded low power SRAM compiler

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Sheng Wu ; Inst. of Microelectron., Tsinghua Univ., Beijing, China ; Xiang Zheng ; Zhiqiang Gao ; Xiangqing He

A highly flexible design methodology of Static Random Access Memory (SRAM) compiler platform is proposed in this paper. With this method, a 65nm CMOS embedded low power single-port SRAM compiler which can generate the whole SRAM IP module files has been developed. A reconfigurable semiautomatic design flow of compiler is obtained, which can be fit for any regular circuits and be more self-adaptive to the migration of technology nodes. According to the design flow, a dual-port SRAM compiler is produced in 65nm process.

Published in:

Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on

Date of Conference:

14-16 April 2010

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.