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Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

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3 Author(s)
Straka, M. ; Fac. of Inf. Technol., Brno Univ. of Technol., Brno, Czech Republic ; Kastil, J. ; Kotasek, Z.

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

Published in:

Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on

Date of Conference:

14-16 April 2010