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Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking

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2 Author(s)
Ghosh, S. ; Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA ; Roy, K.

In this paper, we present a post-silicon self-correction technique to leverage the redundancy present in parallel prefix adders (PPA). Our technique is based on the fact that a set of carries in PPAs can be made mutually exclusive. Therefore, defects in a set of bits can only corrupt the corresponding set of Sum outputs whereas the remaining Sums are computed correctly. To efficiently utilize the above property of PPAs in presence of defects, we perform addition in multiple clock cycles. In cycle-1, one of the correct set of bits are computed and stored at the output registers. In the subsequent cycles, the operands are shifted by one bit at a time and the remaining sets of bits are recovered. This allows us to compute the correct output at the cost of throughput degradation and minor area and delay overhead while maintaining high frequency and yield. Finally, the proposed technique is used in a superscalar processor, whereby the self-correcting adder is assigned lower priority than fault-free adders to reduce the overall throughput degradation.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 8 )