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TSV manufacturing yield and hidden costs for 3D IC integration

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1 Author(s)
Lau, J.H. ; Electron. & Optoelectron. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan

3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general, the TSV (through-silicon-via) separates the 3D IC packaging and 3D IC/Si integrations, i.e., the latter two use TSV, but 3D IC packaging does not. TSV for 3D integration is >26 years old technology, which (with a new concept that every chip could have two active surfaces) is the focus of this study. Emphasis is placed on the TSV manufacturing yield and hidden costs. A 3D integration roadmap is also provided.

Published in:

Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th

Date of Conference:

1-4 June 2010