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Component failures due to physical damage to the silicon are occasionally observed on board assembly processes. Such failures typically are not detected until electrical testing is performed at the end of the process, making it challenging to identify where and how such damages could occur. While process steps are designed to apply the lowest force possible on components, excessive load can be introduced by unexpected events such as machine malfunction or accidental external impact. For over-molded packages, particularly for packages with a large die and thin mold cap thickness, protection for such abnormal impact is reduced and even low levels of force can induce damage to the silicon. In this work, impact test is performed on two types of over-molded packages that have different die and package geometries. External load is applied on the top of the packages through the drop of a probe from different heights. The damages induced in the silicon are evaluated with ultrasonic scan and cross-section. The results from these analytical steps will help identify the threshold force for the die crack failures. A finite element model is constructed to simulate the impact test for one of the packages. The time-history of the load is analyzed and the maximum stress levels in the silicon for the different drop heights are compared. Two different mold cap thicknesses are also simulated. By comparing the stress levels from the model and the real-life testing results, we are able to obtain general guidelines for the maximal impact allowed for the package investigated in this study and provide references for analysis of future failures.