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Evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3D system integration

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12 Author(s)
Zoschke, K. ; Fraunhofer Inst. for Reliability & Microintegration (IZM), Berlin, Germany ; Wegner, M. ; Wilke, M. ; Jürgensen, N.
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In this paper we describe the process integration of a temporary wafer handling system for wafer thinning and thin wafer backside processing. Thin wafer handling is a key technology and enabler for the wafer level fabrication of through silicon via (TSV) based 3D architectures. The work was done as evaluation study to prove the compatibility of a thin wafer handling system with standard processes used for thinning and backside processing of “via-first” TSV wafers as well as for thinning of bumped wafers. The used thin wafer handling system is based on perforated carrier wafers, which are bonded by an adhesive to the customer wafer and de-bonded by solvent release of the adhesive. All wafers used in this work had 200 mm format. The evaluation was run systematically in three major phases. In the first phase the main process scenarios, which require thin wafer handling, were defined. In a second phase setup trials for bonding, thinning, backside processing and de-bonding were run on monitor wafers with different types of front side topography, but without TSVs. After finishing the setup trials in a third phase, the monitor wafers were replaced by wafers with copper filled TSVs, which were fabricated in “via-first” technology. Using the established thin wafer handling and processing sequence, silicon interposer wafers with 55 µm thickness were manufactured. The measured via chains have via pitches of 28 µm using 15 µm via diameter.

Published in:

Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th

Date of Conference:

1-4 June 2010

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