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FPGA based cascaded multilevel pulse width modulation for single phase inverter

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2 Author(s)
Karuppanan, P. ; Nat. Inst. of Technol., Rourkela, India ; Mahapatra, K.K.

This article explores the development of FPGA based controller for conventional and cascaded multilevel PWM single phase inverter. The conventional multilevel inverter is constructed by the H-bridge and cascaded multilevel inverter constructed by two full H-bridges. FPGA logic device is chosen for the hardware implementation of control circuit. VHDL language is used to model the inverter switching strategies. The proposed controller generates 4 and 8 control signals for conventional multilevel inverter and cascaded multilevel inverter respectively. These inverters provide 3-level and 7- level output voltages. Matlab/System generator and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA. These inverter topologies with filters would have reduced harmonics and can operate at high efficiency.

Published in:

Environment and Electrical Engineering (EEEIC), 2010 9th International Conference on

Date of Conference:

16-19 May 2010