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FPGA Implementation of High Performance LDPC Decoder Using Modified 2-Bit Min-Sum Algorithm

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2 Author(s)
Chandrasetty, V.A. ; Sch. of Electr. & Inf. Eng., Univ. of South Australia, Mawson Lakes, SA, Australia ; Aziz, S.M.

In this paper, a reduced complexity Low-Density Parity-Check (LDPC) decoder is designed and implemented on FPGA using a modified 2-bit Min-Sum algorithm. Simulation results reveal that the proposed decoder has improvement of 1.5 dB Eb/No at 10-5 bit error rate (BER) and requires fewer decoding iterations compared to original 2-bit Min-Sum algorithm. With a comparable BER performance to that of 3bit Min-Sum algorithm, the decoder implemented using modified 2-bit Min-Sum algorithm saves about 18% of FPGA slices and can achieve an average throughput of 10.2 Gbps at 4 dB Eb/No.

Published in:

Computer Research and Development, 2010 Second International Conference on

Date of Conference:

7-10 May 2010

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