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Scaling down of amorphous indium gallium zinc oxide thin film transistors on the polyethersulfone substrate employing the protection layer of parylene-C for the large-scale integration

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7 Author(s)
Chang, Seongpil ; Department of Electrical Engineering, Display and Nanosystem Laboratory, Korea University, Seoul 136-713, Republic of Korea ; Ki-Young Dong ; Park, Jung‐Ho ; Oh, Tae-Yeon
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We have investigated the parylene-groups for the device scaling-down as the protection layer of polyethersulfone (PES) substrate. In general, photolithography process on the PES substrate could not be allowed due to its poor chemical resistance. In this work, parylene-C is used as the protection layer. However, adhesion problem is observed caused by the hydrophobic property of parylene-groups. Thereby we additionally used SiO2 as the adhesion layer. Finally, we demonstrated the scaling-down of amorphous indium gallium zinc oxide thin film transistor on a plastic substrate by using lithography technique. Field-effect mobility, threshold voltage, current on-to-off ratio are measured to be 0.84 cm2/Vs, 19.7 V, and 7.62×104, respectively.

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Applied Physics Letters  (Volume:96 ,  Issue: 24 )