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New scaling limitation of the floating gate cell in NAND Flash Memory

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10 Author(s)
Yong Seok Kim ; NAND Flash Process Architecture Team, Semiconductor Business Division, Samsung Electronics Co., San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyunggi-Do 446-711, Korea ; Dong Jun Lee ; Chi Kyoung Lee ; Hyun Ki Choi
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As the scaling in NAND Flash Memory is progressed, the various interferences among the adjacent cells are more and more increased and the new phenomenon which is ignored until now has to be considered. In this paper, we will introduce the new program interference phenomenon which is generated between the program word line and the adjacent word lines along the bit-line. This new program interference is that the Vth's of the adjacent word lines along the bit-line are decreased while a word line is programming. Because this phenomenon is severely aggravated as the gate space is decreased, we have to consider this program interference for the future technology nodes.

Published in:

Reliability Physics Symposium (IRPS), 2010 IEEE International

Date of Conference:

2-6 May 2010