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ESD protection for high-speed receiver circuits

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2 Author(s)
Jack, N. ; Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA ; Rosenbaum, E.

ESD-induced gate oxide breakdown is studied in high-speed receiver circuits. A novel biasing circuit increases the breakdown voltage by modulating the potential of the input transistor's source during ESD. The effectiveness of dual-diode and DTSCR protection of high-speed receiver circuits is examined under various bias conditions.

Published in:

Reliability Physics Symposium (IRPS), 2010 IEEE International

Date of Conference:

2-6 May 2010