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Supply voltage (Vcc) scaling is mostly used method to achieve low power consumption. However, a high Vccmin is required to meet the high target yield because the SRAM yield according to Vcc scaling shows “dual slope”. In this paper, the root causes of “dual slope” are analyzed. Both side effect of SRAM bitcell on the yield is also considered to accurately project Vccmin, which results in 40 mV increase of Vccmin to meet 99% target yield for 32 nm HK/MG planar 1 M SRAM. The “dual slope” effect on the yield is compared for 32nm HK/MG planar and FinFET 32 M SRAMs with high (HD) and low doping (LD). Under the “dual slope” effect, the channel length adjustment method for pass gate transistor is proposed to reduce Vccmin of FinFET SRAM. When the number of finis is 1:2:2 (=PU:PG:PD), HD and LD 32 M FinFET SRAMs improve Vccmin by 370 mV and 500 mV, respectively, compared to 32 M planar counterparts using the proposed the channel length adjustment method. Effect of NBTI and PBTI on Vccmin is also investigated. BTI degradation is greatly dependent on HK thickness and surface plane orientation of FinFET. End of Life (EOL) Vccmin optimization therefore requires careful selection of HK thickness and surface orientation.