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NBTI stress relaxation design for scaling high-voltage transistors in NAND Flash memories

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1 Author(s)
Toru Tanzawa ; Flash Design Center, Micron Japan, Ltd., 5-37-1, Kamata, Ota-ku, Tokyo 144-8721, Japan

For decades, advances in lithography and improvements in device technology have been scaling the NAND Flash memory cells in L and W directions. On the other hand, Z direction, or tunnel oxide thickness, has not been scaled. This is because of stress-induced leakage current that results in program and erase voltages and high-voltage (HV) transistors unscaled. This paper focuses on scaling the HV transistors with a proposed circuit design relaxing the gate stress. The proposed circuit enables the gate oxide thickness of HV transistors to be reduced by 10%, which results in a die size reduction of 2.4%. This paper also proposes a simple estimation equation for HV PMOS negative bias temperature instability (NBTI) lifetime in case of step-up programming pulses.

Published in:

2010 IEEE International Memory Workshop

Date of Conference:

16-19 May 2010