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Through-silicon-via technology for 3D integration

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35 Author(s)
Dukovic, J. ; Silicon Syst. Group, Appl. Mater. Inc., Santa Clara, CA, USA ; Ramaswami, S. ; Pamarthy, S. ; Yalamanchili, R.
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Major efforts are currently underway throughout the IC industry to develop the capability to integrate device chips by stacking them vertically and using through-silicon vias (TSVs). The resulting interconnect density, bandwidth, and compactness achievable by TSV technology exceed what is currently possible by other packaging approaches. Market-driven applications of TSV involving memory include multi-chip high-performance DRAM, integration of memory and logic functions for enhanced video on handheld devices, and stacked NAND flash for solid-state drives. High-volume commercial implementation of 3D TSV is imminent but faced by special challenges of design, fabrication, bonding, test, reliability, know-good die, standards, logistics, and overall cost. The main focus of this paper is the unit-process and process-integration technology required for TSV fabrication at the wafer level: deep silicon etching, dielectric via isolation, metallization, metal fill, and chemical-mechanical polishing.

Published in:

Memory Workshop (IMW), 2010 IEEE International

Date of Conference:

16-19 May 2010

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