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Technology challenges for deep-nano semiconductor

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1 Author(s)
Kim, Kinam ; Samsung Adv. Inst. of Technol., Samsung Electron. Co., Ltd., Yongin, South Korea

The rapid evolution of flash memory technologies in the previous decade has been achieved through the two distinctive ways; overcoming the scaling challenges and devising multi-bit cell transistors. The scaling challenges such as cell-to-cell interference, cell programming disturbance and patterning limit have been tackled with several breakthroughs; incorporating low-k material, relieving the stress on tunnel oxide and double patterning technology (DPT). Multi-bit cell transistors have multiplied the chip density up to 4 times with the new circuit technology and the controller algorithms. And now, the key technology in the sub-20nm technology region is finding how to integrate all the available solutions of process, device, circuit and controller issues with the most efficient ways. In the aspect of integrating each technology, we discuss technical scaling barrier in sub-20nm region and present the future candidate for high-density devices.

Published in:

Memory Workshop (IMW), 2010 IEEE International

Date of Conference:

16-19 May 2010