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The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the Extended Sidewall Control Gate (ESCG)

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3 Author(s)
Moon-Sik Seo ; Center for Interdisciplinary Research, Tohoku University; 6-3 Aramaki-aza-Aoba, Aoba-ku, Sendai, Miyagi, 980-8578, Japan ; Sung-kye Park ; Tetsuo Endoh

We propose the novel 3-dimensional (3-D) vertical floating gate (FG) NAND flash memory cell arrays with novel electrical source/drain (S/D) technique using Extended Sidewall Control Gate (ESCG). Cylindrical FG structure cell is implemented to overcome the reliability issues of the charge trap cell such as SONOS and TANOS cell. We also propose the novel electrical S/D layer using the ESCG structure to realize the enhancement mode operation. Using this novel structure, we successfully demonstrate the normal flash cell operation with high-speed programming and superior read current due to both the increasing of coupling ratio and low resistive electrical S/D technique. Moreover, we found that the 3-D vertical flash memory cell array with novel electrical S/D technique had less interference with neighboring cells by about 50% in comparison with planar FG NAND cell. From above all, the proposed cell array is one of the candidates of Terabit 3-D vertical NAND flash cell array with high-speed read/program operation and high reliability.

Published in:

2010 IEEE International Memory Workshop

Date of Conference:

16-19 May 2010