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This paper presents a high speed real-time target detection system for non homogenous environment based on FPGA Technology. The system implements a Backward Automatic Censored Ordered Statistics Detector (B-ACOSD) to maintain a Constant False Alarm Rate (CFAR) for Radar system with a time constraints in term of signal computing and target identification. The design flow and the hardware implementation of each module are introduced in detail. The proposed system can operate up to 115 MHz by using full pipeline organization and parallel computing which increase the speed up of the target detection system to satisfy the real-time constraints. The proposed architecture is designed, implemented, and tested using Stratix II EP2S60F672C3N FPGA Board. The system has the advantages of being simple, fast, and flexible with low development cost for a reference window of length 16 cells.