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MDAC design for 1.5-bit pipeline stage of high-speed high-resolution ADC

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3 Author(s)
Zhang Guo-min ; Institute of VLSI Design, Hefei University of Technology, China ; Yin Yong-sheng ; Deng Hong-hui

This paper presents a design of residue amplification circuit (MDAC) used in the first 1.5-bit pipeline stage of an ADC, and the MDAC should meet requirements of a 100MS/s 14-bit pipeline ADC with 1.8V supply voltage. In order to obtain the corresponding performance, the circuits such as operational amplifier and bootstrap circuit are designed which could realize the objective of high-speed and high-resolution. The gain-boost structure is used in the amplifier to obtain the specified resolution, and an optimization between speed and power dissipation should be carefully conducted as a high speed requires a large slew rate or trans-conductance which is proportional to power dissipation. The design is implemented in the 0.18μm CMOS process with 9.6mW power consumption and the simulation results in Spectre illustrate that, the designed operational amplifier could reach the fixed objective and the residue signal of MDAC could set up completely in the specified time 3ns.

Published in:

Advanced Computer Control (ICACC), 2010 2nd International Conference on  (Volume:1 )

Date of Conference:

27-29 March 2010